Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, calculating the of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For first time, parameters model are obtained from measurements ac conductance characteristic frequency determination. The shows decreasing resistance linearly augmented capacitance with increasing length 0.18 2.50 $\mu \text{m}$ . Thus, time constants ~760 ns, extracted a variety lengths, correctly predicted.